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description the m pd78p018f is an 8-bit single-chip microcomputer which incorporates one-time prom which can be written to once only, or eprom to which programs can be written, erased and rewritten. as the m pd78p018f is user-programmable, it is suitable for evaluation in system development, and for short-run and multiple device-production, and early start-up. this document should be read in conjunction with documentation on the mask rom products. features y pin compatible with mask rom products (except v pp pin) y internal prom: 60k bytes *1 y internal high-speed ram: 1024 bytes *1 y internal expansion ram : 1024 bytes *2 y buffer ram: 32 bytes y operable over same supply voltage range as mask rom product (2.0 to 6.0 v) *1. the internal prom and internal high-speed ram size can be changed by means of the memory size switching register. 2. the capacity of the internal expansion ram can be changed by means of the internal expansion ram switching register. mos integrated circuit m pd78p018f 8-bit single-chip microcomputer preliminary product information ? nec corporation 1993 document no. (o. d. no. ip-8887) date published november 1993 p printed in japan differences from mask rom products are as follows: ? the same memory mapping as on a mask rom product is possible by setting the memory size switching register and the internal expansion ram switching register. ? there is no function for incorporating pull-up resistors by means of a mask option. the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. in this document, the common parts of the one-time prom product and eprom product are represented by prom.
2 m pd78p018f ordering information ordering code package internal rom m pd78p018fcw 64-pin plastic shrink dip (750 mil) one-time prom m pd78p018fdw 64-pin ceramic shrink dip (with window) (750 mil) eprom m pd78p018fgc-ab8 64-pin plastic qfp ( 14 mm) one-time prom m pd78p018fgk-8a8 64-pin plastic qfp ( 12 mm) one-time prom m pd78p018fkk-s 64-pin ceramic wqfn ( 14 mm) eprom quality grade standard 78k/0 series development y series products are compatible with i 2 c bus. m pd78064 series 100-pin package lcd controller/driver, uart added 16-bit timer/event counter function enhanced m pd78054y series m pd78054 series 80-pin package uart, d/a converter, real-time output port added 16-bit timer/event counter function enhanced m pd78064y series m pd78044y series 80-pin package automatic transmission/reception function added 6-bit up/down counter added fip controller/driver function enhanced 64-pin package a/d converter, 16-bit timer/event counter, fip ? controller/driver, multiplication/division instruction added m pd78024 series m pd78024y series m pd78002y series 64-pin package m pd78014y series 64-pin package sio with a/d converter, 16-bit timer/event counter, automatic transmission/reception function added multiplication/division instruction added products under development products in volume production m pd78044 series m pd78014 series m pd78002 series please refer to "quality grade on nec semiconductor devices" (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
3 m pd78p018f outline of function ? prom : 60k bytes *1 ?ram internal high-speed ram : 1024 bytes *1 internal expansion ram : 1024 bytes *2 buffer ram : 32 bytes 64k bytes 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip instruction execution time cycle modification function 0.48 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz operation) 122 m s (at 32.768 khz operation) ? 16-bit operation ? multiplication/division (8 bits 8 bits,16 bits 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd correction, etc. total : 53 ? cmos input : 2 ? cmos i/o : 47 ? n-channel open-drain i/o (15 v withstand voltage) : 4 ? 8-bit resolution 8 channels ? operable over a wide power supply voltage range: v dd = 2.0 to 6.0 v ? 3-wire/sbi/2-wire mode selectable : 1 channel ? 3-wire mode (on-chip max. 32 bytes automatic data transmit/receive function) : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? clock timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (at main system clock 10.0 operation) 32.768 khz (at subsystem clock 32.768 khz operation) 2.4 khz, 4.9 khz, 9.8 khz (at main system clock 10.0 mhz operation) internal : 8, external : 4 internal : 1 internal : 1 internal : 1, external : 1 v dd = 2.0 to 6.0 v -40 to +80 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin ceramic shrink dip (with window) (750 mil) ? 64-pin plastic qfp ( 14 mm) ? 64-pin plastic qfp ( 12 mm) ? 64-pin ceramic wqfn ( 14 mm) internal memory memory space general registers instruction cycle instruction set i/o ports a/d converter serial interface timer timer output clock output buzzer output vectored interrupts test input operating voltage range operating tempreture range package item function main system clock selected subsystem clock selected *1. the capacity of the internal prom and internal high-speed ram can be changed by means of the memory size switching register. 2. the capacity of the internal expansion ram can be changed by means of the internal expansion ram switching register. maskable non-maskable software
4 m pd78p018f pin configuration (top view) (1) normal operating mode 64-pin plastic shrink dip (750 mil) 64-pin ceramic shrink dip (with window) (750 mil) 1 p20/si1 2 p21/so1 3 p22/sck1 4 p23/stb 5 p24/busy 6 p25/si0/sb0 7 p26/so0/sb1 8 p27/sck0 9 p30/to0 10 p31/to1 11 p32/to2 12 p33/ti1 13 p34/ti2 14 p35/pcl 15 p36/buz 16 p37 17 v ss 18 p40/ad0 19 p41/ad1 20 p42/ad2 21 p43/ad3 22 p44/ad4 23 p45/ad5 24 p46/ad6 25 p47/ad7 26 p50/a8 27 p51/a9 28 p52/a10 29 p53/a11 30 p54/a12 31 p55/a13 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 av ref av dd p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ss p04/xt1 xt2 v pp x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0/ti0 reset p67/astb p66/wait p65/wr p64/rd p63 p62 p61 p60 p57/a15 p56/a14 m pd78p018fcw m pd78p018fdw note 1. v pp pin should be connected to v ss . 2. av dd pin should be connected to v dd . 3. av ss pin should be connected to v ss .
5 m pd78p018f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p11/ani1 p10/ani0 av ss p04/xt1 xt2 v pp x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0/ti0 reset p67/astb p66/wait p37 v ss p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/sck0 p26/so0/sb1 p25/si0/sb0 p24/busy p23/stb p22/sck1 p21/so1 p20/si1 av ref av dd p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd p65/wr 64-pin plastic qfp ( 14 mm) 64-pin plastic qfp ( 12 mm) 64-pin ceramic wqfn ( 14 mm) m pd78p018fgc-ab8 m pd78p018fgk-8a8 m pd78p018fkk-s note 1. v pp pin should be connected to v ss . 2. av dd pin should be connected to v dd . 3. av ss pin should be connected to v ss .
6 m pd78p018f ad0 to ad7 : address/data bus a8 to a15 : address bus rd : read strobe wr : write strobe wait : wait astb : address strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) reset : reset ani0 to ani7 : analog input av dd : analog power supply av ss : analog ground av ref : analog reference voltage v dd : power supply v pp : programming power supply v ss : ground p00 to p04 : port 0 p10 to p17 : port 1 p20 to p27 : port 2 p30 to p37 : port 3 p40 to p47 : port 4 p50 to p57 : port 5 p60 to p67 : port 6 intp0 to intp3 : interrupt from peripherals ti0 to ti2 : timer input to0 to to2 : timer output sb0, sb1 : serial bus si0, si1 : serial input so0, so1 : serial output sck0, sck1 : serial clock pcl : programmable clock buz : buzzer clock stb : strobe busy : busy
7 m pd78p018f note 1. (l) : connect to v ss individually with a pull-down resistor. 2. v ss : connect to ground. 3. reset : set to low level. 4. open : do not make any connection. (2) prom programming mode 64-pin plastic shrink dip (750 mil) 64-pin ceramic shrink dip (with window) (750 mil) 1 2 3 4 5 6 7 8 9 d0 10 d1 11 d2 12 d3 13 d4 14 d5 15 d6 16 d7 17 v ss 18 a0 19 a1 20 a2 21 a3 22 a4 23 a5 24 a6 25 a7 26 a8 27 a16 28 a10 29 a11 30 a12 31 a13 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss v dd v ss (l) open v pp (l) open v dd a9 reset ce oe a14 (l) (l) (l) (l) a15 (l) pgm (l) m pd78p018fcw m pd78p018fdw
8 m pd78p018f note 1. (l) : connect to v ss individually with a pull-down resistor. 2. v ss : connect to ground. 3. reset : set to low level. 4. open : do not make any connection. 64-pin plastic qfp ( 14 mm) 64-pin plastic qfp ( 12 mm) 64-pin ceramic wqfn ( 14 mm) m pd78p018fgc-ab8 m pd78p018fgk-8a8 m pd78p018fkk-s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ss (l) open v pp (l) open v dd a9 reset d7 v ss d0 d1 d2 d3 d4 d5 d6 a0 a1 a2 a3 a4 a5 a6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss v dd a7 a8 a16 a10 a11 a12 a13 v ss a14 oe ce (l) (l) (l) (l) (l) (l) pgm (l) a15 reset : reset v dd : power supply v pp : programming power supply v ss : ground a0 to a16 : address d0 to d7 : data bus ce : chip enable oe : output enable pgm : program
9 m pd78p018f block diagram p00-p04 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 port0 port1 port2 port3 port4 port5 port6 external access general reg. ram data memory 2080 x 8 decode and control prom program memory 61440 x 8 program counter 16 bit timer/ event counter 8 bit timer/ event counter 1 18 bit timer/ event counter 2 watchdog timer watch timer serial interface 0 serial interface 1 a/d converter interrupt control to0/p30 alu psw sp buzzer output clock output control clock divider clock generator sub main stand by control buz/p36 pcl/p35 p04/xt1 xt2 x1 x2 reset v pp v ss ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10 -ani7/p17 av dd av ss av ref intp0/p00 -intp3/p03 v dd so0/sb1/p26 sck0/p27
10 m pd78p018f contents 1. differences between m pd78p018f and mask rom product .................................................. 11 2. pin functions .............................................................................................................................................. 12 2.1 normal operating mode pins ......................................................................................................... 12 2.2 prom programming mode pins ....................................................................................................... 15 2.3 pin input/output circuits and connection of unused pins ................................................ 16 3. memory size switching register (ims) ........................................................................................... 18 4. internal expansion ram switching register (ixs) ................................................................. 19 5. prom programming ................................................................................................................................. 20 5.1 operating modes ................................................................................................................................. 20 5.2 prom writing procedure .................................................................................................................. 22 5.3 prom reading procedure ................................................................................................................. 26 6. erasure procedure ( m pd78p018fdw/78p018fkk-s) ...................................................................... 27 7. erasure window seal ( m pd78p018fdw/78p018fkk-s) ................................................................. 27 8. one-time prom poroduct screening .............................................................................................. 27 9. package information ............................................................................................................................. 28 appendix a. development tools .............................................................................................................. 33 appendix b. related documents .............................................................................................................. 36
11 m pd78p018f 1. differences between m pd78p018f and mask rom product the m pd78p018f incorporates one-time prom which can be written to once only, or eprom to which programs can be written, erased and rewritten. by setting the memory size switching register and internal expansion ram switching register it is possible to make the functions of this device, except for the prom specification and mask option for pins p60 to p63, identical to those of a mask rom product. the differences between the m pd78p018f and mask rom products are shown in table 1-1. table 1-1 differences between m pd78p018f and mask rom product m pd78p018f ic pin v pp pin mask option for pins p60 to p63 no yes no mask option for incorporation of pull- up resistor yes no pull-up resistor incorporation possible by means of mask option item mask rom product note 1. in the m pd78p018f, the capacity of the internal prom and internal high-speed ram can be changed by means of the memory size switching register. after reset input, the internal prom capacity is 60k bytes, and the internal high-speed ram capacity is 1k bytes. 2. in the m pd78p018f, the capacity of the internal expansion ram can be changed by means of the internal expansion ram switching register. the internal expansion ram is set to 1k bytes by means of reset input.
12 m pd78p018f 2. pin functions 2.1 normal operating mode pins (1) port pins (1/2) dual- function pin intp0/ti0 intp1 intp2 intp3 xt1 ani0 to ani7 si1 so1 sck1 stb busy si0/sb0 so0/sb1 sck0 to0 to1 to2 ti1 ti2 pcl buz ad0 to ad7 p00 p01 p02 p03 p04 *1 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 function pin name i/o port 0 5-bit i/o port input port 1 8-bit input/output port. input/output can be specified in 1-bit unit. when used as an input port, pull-up resistor can be used by software. *2 input/ output input/ output port 2 8-bit input/output port. input/output can be specified in 1-bit unit. when used as an input port, pull-up resistor can be used by software. port 3 8-bit input/output port. input/output can be specified in 1-bit unit. when used as an input port, pull-up resistor can be used by software. input/ output input/ output input/ output input only input/output can be specified in 1-bit unit. when used as an input port, pull-up resistor can be used by software. input only input after reset input input input input input input input port 4 8-bit input/output port. input/output can be specified in 8-bit unit. when used as an input port, pull-up resistor can be used by software. test flag (krif) is set to 1 by falling edge detection. *1. when using the p04/xt1 pins as an input port, set 1 in bit 6 (frc) of the processor clock control register and do not use the internal feedback resistor of the subsystem clock oscillator. 2. when pins p10/ani0 to p17/ani7 are used as analog inputs of the a/d converter, the use of the pull-up resistor is automatically disabled.
13 m pd78p018f a8 to a15 rd wr wait astb (1) port pins (2/2) dual- function pin p60 p61 p62 p63 p64 p65 p66 p67 function pin name i/o port 5 8-bit input/output port. led can be driven directly. input/output can be specified in 1-bit unit. when used as an input port, pull-up resistor can be used by software. p50 to p57 after reset input port 6 8-bit input/output port. input/output can be specified in 1-bit unit. n-ch open-drain input/ output port. led can be driven directly. when used as an input port, pull-up resistor can be used by software. input input/ output input/ output
14 m pd78p018f p00/ti0 p01 p02 p03 p25/sb0 p20 p26/sb1 p21 p25/si0 p26/so0 p27 p22 p23 p24 p00/intp0 p33 p34 p30 p31 p32 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 intp0 intp1 intp2 intp3 si0 si1 so0 so1 sb0 sb1 sck0 sck1 stb busy ti0 ti1 ti2 to0 to1 to2 pcl buz ad0 to ad7 a8 to a15 rd wr wait astb (2) non port pins (1/2) dual- function pin function pin name i/o external interrupt input with specifiable valid edge (rising edge, falling edge, or both rising edge and falling edges). falling edge detection external interrupt input. serial interface serial data input. output serial interface serial data output. serial interface serial data input/output. after reset input input input input input input input input serial interface serial clock input/output input serial interface automatic transmission/reception strobe output. serial interface automatic transmission/reception busy input. input input of external count clock to 16-bit timer (tm0). input of external count clock to 8-bit timer (tm1). input of external count clock to 8-bit timer (tm2). 16-bit timer output (dual-function with 14-bit pwm output) 8-bit timer output clock output (for main system clock subsystem clock trimming). buzzer output. low address/data bus when memory is expanded externally. high address bus when memory is expanded externally. external memory read operation strobe signal output. external memory write operation strobe signal output. wait insertion at external memory access. input input input output output of strobe which externally latches address information to be output to port 4 when accessing external memory. input input input input input input input/ output input/ output output input input output output output input/ output output input output
15 m pd78p018f prom programming mode setting. when +5 v or +12.5 v is applied to the v pp pin and a low-level signal to the reset pin, the prom programming mode is set. prom programming mode setting and high voltage application for program write/verify. address bus. data bus. prom enable input/program pulse input. prom read strobe input. prom programming mode program/program inhibit input. positive power supply. ground potential. input input input input input a/d converter analog input. a/d converter reference voltage input. a/d converter analog power supply. connected to v dd . a/d converter ground potential. connected to v ss . system reset input. main system clock oscillation crystal connection. subsystem clock oscillation crystal connection. positive power supply. ground potential dual- function pin function pin name i/o ani0 to ani7 av ref av dd av ss reset x1 x2 xt1 xt2 v dd v pp v ss p10 to p17 p04 (2) non port pins (2/2) after reset input input high voltage application for program write/verify. connected v ss in normal operating mode. function pin name i/o reset v pp a0 to a16 d0 to d7 ce oe pgm v dd v ss 2.2 prom programming mode pins input input input input/ output input input input
16 m pd78p018f 2.3 pin input/output circuits and connection of unused pins the input/output circuit type of each pin and the recommended connection of unused pins are shown in table 2-1. the configuration of each type of input/output circuit is shown in fig. 2-1. table 2-1 input/output circuit type of each pin leave open. connected to v ss . connected to v dd . connected to v ss . p00/intp0/ti0 p01/intp1 p02/intp2 p03/intp3 p04/xt1 p10/ani0 to p17/ani7 p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60 to p63 p64/rd p65/wr p66/wait p67/ astb reset xt2 av ref av dd av ss v pp input/output circuit type 2 8-a 16 11 8-a 5-a 8-a 5-a 8-a 10-a 5-a 8-a 5-a 5-e 5-a 13 5-a 2 16 input input/output input input/output input/output input/output input/output input/output input i/o pin name connected to v ss . input : connected to v ss . output : leave open. connected to v ss . input : connected to v dd or v ss . output : leave open. input : connected to v dd or v ss . output : leave open. input : connected to v dd or v ss . output : leave open. input : connected to v ss . output : leave open. input : connected to v dd or v ss . output : leave open. recommended connection when not used
17 m pd78p018f fig. 2-1 pin input/output circuits type 10-a type 11 type 13 data output disable n-ch in / out middle-high voltage input buffer pullup enable data output disable in / out n-ch v ref input enable dd (threshold voltage) v p-ch n-ch p-ch dd v p-ch + - comparator pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd open drain type 2 in pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd type 5-a input enable type 5-e pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd schmitt-triggered input with hysteresis characteristic type 8-a pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd type 16 in (xt1) feed back cut-off p-ch out (xt2 )
18 m pd78p018f 3. memory size switching register (ims) this register is used to prevent part of the internal memory from being used by software. setting the memory size switching register (ims) enables memory mapping identical to that of a mask rom product w ith different internal memory (rom and ram) to be used. ims is set by an 8-bit memory manipulation instruction. reset input sets this register to cfh. fig. 3-1 memory size switching register format symbol 7 6 5 4 3 2 1 0 address after reset r/w fff0h cfh w ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 rom3 rom2 rom1 rom0 internal rom capacity selection 00108k bytes 010016k bytes 011024k bytes 100032k bytes 101040k bytes 110048k bytes 111160k bytes setting prohibited internal high-speed ram capacity selection 000768 bytes 001640 bytes 010512 bytes 011384 bytes 100256 bytes 1 0 1 setting prohibited 1 1 0 1024 bytes 111896 bytes ims set value relevant mask rom product c6h c8h cch m pd78013f * m pd78014f * m pd78016f * the ims set values to make the memory map identical to various mask rom products are shown in table 3-1. table 3-1 examples of memory size switching register settings * under development other than above ram2 ram1 ram0
19 m pd78p018f 10101024 bytes (f400h to f7ffh) 1011512 bytes (f600h to f7ffh) 11000 bytes setting prohibited 4. internal expansion ram switching register (ixs) this register is used to prevent part of the internal expansion ram from being used by software. setting the internal expansion ram switching register enables memory mapping identical to that of a mask rom product with different internal expansion ram to be used. ixs is set by an 8-bit memory manipulation instruction. reset input sets this register to 0ah. 7 6 5 4 3 2 1 0 address after reset r/w fff4h 0ah w ixs0000ixixixix ram3 ram2 ram1 ram0 ix ix ix ix ram3 ram2 ram1 ram0 other than above internal expansion ram capacity selection
20 m pd78p018f h h l l x x l l h page data latch page write byte write program verify program inhibit read output disable standby 5. prom programming the m pd78p018f incorporates a 60k-byte prom as program memory. when programming the m pd78p018f, the prom programming mode is set by means of the v pp and reset pins. for the connection of unused pins, see pin configuration, (2) prom programming mode . 5.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, the m pd78p014 enters the programming mode. this is one of the operating modes shown in table 5-1 below according to the setting of the ce, oe and pgm pins. also, the prom contents can be read by setting the read mode. data input high impedance data input data output high impedance data output high impedance high impedance operating mode reset v pp v dd d0 to d7 pins table 5-1 prom programming operating modes ce oe l h h l h l l h x pgm h l l h h l h x x l +5 v +5 v +6.5 v +12.5 v remarks x : l or h.
21 m pd78p018f (1) read mode read mode is set by setting ce = l or oe = l. (2) output disable mode setting oe = h makes the data output high impedance, and sets the output disable mode. therefore, when more than one m pd78p018f is connected to the data bus, data can be read from any of the devices by controlling the oe pin. (3) standby mode standby mode is set by setting ce = h. in this mode, the data output becomes high impedance regardless of the oe conditions. (4) page data latch mode page data latch mode is set by setting ce = h, pgm = h and oe = l at the beginning of the page write mode. in this mode, data of 4 bytes per page is latched in the internal address/data latch circuit. (5) page write mode after address and data of 4 bytes per page have been latched in the page data latch mode, page write is performed by applying a 0.1 ms program pulse (active low) to the pgm pin with ce = h, oe = h. program verify can then be performed by setting ce = l, oe = l. if programming cannot be performed with one program pulse, write and verify should be repeated x times (x - 10). (6) byte write mode a byte write is performed by applying a 0.1 ms program pulse (active low) to the pgm pin with ce = l, oe = h. a program verify can then be performed by setting oe = l. if programming cannot be performed with one program pulse, write and verify should be repeated x times (x - 10). (7) program verify mode program verify mode is set by setting ce = l, pgm = h and oe = l. after a write has been executed, verification should be performed to ensure a correct write is achieved in this mode. (8) program inhibit mode when the oe pin, v pp pin and d0 to d7 pins are connected in parallel in more than one m pd78p018f, program inhibit mode is used in the case where a writing is performed to one of these devices. the write mode or byte write mode above is used for writing. writing is not performed to a device whose pgm pin has been driven high.
22 m pd78p018f 5.2 prom write procedure fig. 5-1 page program mode flowchart remarks 1. g indicates start address. 2. n indicates program final address. start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 address = n? latch v dd = 4.5 - 5.5 v, v pp = v dd verify of all bytes write completed defective device all pass address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 0.1 ms program pulse verify 4 bytes address = address + 1 x = 10? yes pass no pass fail yes no fail
23 m pd78p018f fig. 5-2 page program mode timing a2-a16 a0, a1 d0-d7 v pp v dd ce pgm oe v pp v dd + 1.5 v ih v ih v ih v dd v dd v il v il v il page data latch page program program verify data input data output
24 m pd78p018f fig 5-3 byte program mode flowchart remarks 1. g indicates start address. 2. n indicates program final address. start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 address = n? x = x + 1 v dd = 4.5 - 5.5 v, v pp = v dd verify of all bytes write completed defective device all pass 0.1 ms program pulse verify x = 10? yes pass no pass fail yes no fail address = address + 1
25 m pd78p018f fig 5-4 byte program mode timing a0-a16 program program verify d0-d7 v pp v dd ce pgm oe v pp v dd + 1.5 v ih v ih v ih v dd v dd v il v il v il data input data output note 1. v dd should be applied before v pp and disconnected after v pp . 2. v pp including overshoot should not exceed +13.5 v. 3. removal and reinsertion while +12.5 v is applied to v pp may have an adversary effect on reliability.
26 m pd78p018f 5.3 prom reading procedure prom contents can be read onto the external data bus (d0 to d7) using the following procedure. (1) fix the reset pin low. supply +5 v to the v pp pin. unused pins are handled as shown in pin con- figuration, (2) prom programming mode . (2) supply +5 v to the v dd and v pp pins. (3) input address of data to be read to pins a0 to a14. (4) read mode . (5) output data to pins d0 to d7. timing for steps (2) to (5) above is shown in fig. 5-5. fig. 5-5 prom read timing a0-a16 address input ce (input) oe (input) d0-d7 data output hi-z hi-z
27 m pd78p018f 6. erasure procedure ( m pd78p018fdw/78p018fkk-s) with the m pd78p018fdw/78p018fkk-s, it is possible to erase (set to ffh) data written to the program memory, and rewrite the memory. the data can be erased by irradiating the window with light with a wavelength of approximately 400 nm or less. usually, irradiation is performed with ultraviolet light with a wavelength of 254 nm. the amount of radiation required for complete erasure is shown below. ? uv intensity x erasure time: 15 w ? s/cm 2 or more ? erasure time: 15 to 20 minutes (using a 12,000 m w/cm 2 ultraviolet lamp. a longer erasure time may be required in case of deterioration of the ultraviolet lamp or dirt on the package window). erasure should be carried out with the ultraviolet lamp placed at a distance of 2.5 cm or less from the window. if the ultraviolet lamp is fitted with a filter, this should be removed before performing irradiation. 7. erasure window seal ( m pd78p018fdw/78p018fkk-s) a protective seal should be applied to the erasure window except when erasing the eprom contents, in order to prevent the eprom contents from being erroneously erased by light other than from the erasure lamp, and the internal circuits other than eprom from misoperation due to light. 8. one-time prom product screening one-time prom products ( m pd78p018fcw/78p018fgc-ab8/78p018fgk-8a8) cannot be fully tested and shipped by nec for reasons related to their structure. it is recommended that after writing the necessary data and storing at high temperature under the following conditions, screening should be conducted to verify the prom. storage temperature duration 125 c 24 hours
28 m pd78p018f 9. package information 64-pin plastic shrink dip (750 mil)
29 m pd78p018f 64-pin ceramics shrink dip (750 mil)
30 m pd78p018f 64-pin plastic qfp ( 14)
31 m pd78p018f k j n a m f b 48 49 32 l 64 pin plastic qfp ( 12) 64 1 17 16 33 g detail of lead end s q 55 h d c p m i p64gk-65-8a8 item millimeters inches a b c d f g h i j k l 14.8 0.4 12.0 0.2 1.125 0.30 0.10 0.13 12.0 0.2 0.583 0.016 0.044 0.044 0.005 0.026 (t.p.) 0.472 note m n 0.10 0.15 1.4 0.2 0.65 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.055 0.008 0.012 0.472 0.6 0.2 0.024 p 1.4 0.055 0.583 0.016 14.8 0.4 1.125 +0.008 ?.009 q 0.1 0.1 0.004 0.004 s 1.7 max. 0.067 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 64-pin plastic qfp ( 12)
32 m pd78p018f 64-pin ceramic wqfn ( 14) in preparation
33 m pd78p018f 78k/0 series common in-circuit emulator 78k/0 series common break board m pd78002/78014 series common evaluation emulation board m pd78244 series common emulation probes ie-78000-r screen debugger m pd78014 series common device file appendix a. development tools the following development tools are available for system development using the m pd78p018f. language processing software ra78k/0 *1,2 cc78k/0 *1,2 cc78k/0-l *1,2 78k/0 series common assembler package 78k/0 series common c compiler package 78k/0 series common c compiler library source file prom writing tools prom programmer pg-1500 control program pg-1500 pa-78p018cw *3 pa-78p018gc *3 pa-78p018gk *3 pa-78p018kk-s *3 pg-1500 controller *1 debugging tools ie-78000-r ie-78000-r-bk ie-78014-r-em-a *3 ep-78240cw-r ep-78240gc-r ep-78012gk-r ev-9200gc-64 ev-9500gk-64 sd78k/0 *1 df78014 *1 real-time os 78k/0 series common real-time os rx78k/0 *1,2 fuzzy inference development support system fuzzy knowledge data creation tool translator fuzzy inference module fuzzy inference debugger fe9000 *1 ft9080 *1 fi78k0 *1 fd78k0 *1,3 *1. pc-9800 series (ms-dos tm ) based and ibm pc/at tm (pc-dos tm ) based 2. hp9000 series 300 tm (hp-ux tm ) based, sparcstation tm (sun os tm ) based, ews-4800 series tm (ews-ux/v tm ) based 3. under development programmer adapters connected to pg-1500 sockets to be mounted on a user system board made for 64-pin plastic qfp
34 m pd78p018f conversion socket (ev-9200gc-64) external view and recommended board mounting pattern fig. a-1 ev-9200gc-64 external view (reference)
35 m pd78p018f fig. a-2 ev-9200gc-64 recommended board mounting pattern (reference) note the mount pad dimensions for ev-9200 may be partially different from those (for qfp) of the relevant products. refer to " surface mount technology manual, iei-1207" for recommended qfp mount pad dimensions.
36 m pd78p018f appendix b. related documents device related documents document no. (japanese) to be created to be created to be created to be created iea-715 iea-740 iea-718 document name user's manual instruction application table instruction set special function register application table application note introductory volume i introductory volume ii floating-point operation program volume development tool documents (user's manuals) document no. (japanese) eeu-809 eeu-815 eeu-817 eeu-656 eeu-655 eeu-777 eeu-651 eeu-704 eeu-810 eeu-867 to be created eeu-852 eeu-816 document name ra78k series structured assembler preprocessor cc78k series library source file pg-1500 prom programmer pg-1500 controller ie-78000-r ie-78000-r-bk ie-78014-r-em-a operation volume language volume operation volume language volume primer reference ra78k series assembler package cc78k series c compiler sd78k/0 screen debugger note for design purposes, etc., be sure to use the latest documents.
37 m pd78p018f document no. (japanese) eeu-912 eeu-911 eeu-930 eeu-913 eeu-829 eeu-858 eeu-921 document name fuzzy knowledge data creation tools 78/0, 78k/ii, 87ad series fuzzy inference development support system translator 78k/0 series fuzzy inference development support system fuzzy inference module 78k/0 series fuzzy inference development support system fuzzy inference debugger built-in software documents (user's manuals) introductory volume installation volume debugger volume technical volume document no. (japanese) iei-635 iei-616 iei-620 iem-5068 mem-539 mei-603 mei-604 document name package manual surface mount technology manual quality grades on semiconductor devices nec semiconductor device reliability & quality control electrostatic discharge (esd) test semiconductor devices quality control guarantee guide microcomputer related products guide other manufacturers volume other documents 78k/0 series real-time os note for design purposes, etc., be sure to use the latest documents. eeu-862
[memo] m pd78p018f no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92.6 fip is a trademark of nec corporation. ews-4800 series and ews-ux/v are trademarks of nec corporation. ms-dos is a trademark of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 300 and hp-ux are trademarks of hewlett-packard company. sparc station is a trademark of sparc international, inc. sun os is a trademark of sun microsystems corporation.

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